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570 lines
18 KiB
570 lines
18 KiB
/**
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******************************************************************************
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* @file py32f0xx_hal_rcc_ex.c
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* @author MCU Application Team
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* @brief Extended RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities RCC extended peripheral:
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* + Extended Peripheral Control functions
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* + Extended Clock management functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2023 Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by Puya under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "py32f0xx_hal.h"
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/** @addtogroup PY32F0xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCCEx RCCEx
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* @brief RCC Extended HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private defines -----------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
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* @{
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*/
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#define PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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* @{
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*/
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/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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* @brief Extended Peripheral Control functions
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*
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@verbatim
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===============================================================================
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##### Extended Peripheral Control functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to control the RCC Clocks
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frequencies.
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[..]
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(@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to
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select the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) and RCC_BDCR register are set to their reset values.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initialize the RCC extended peripherals clocks according to the specified
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* parameters in the @ref RCC_PeriphCLKInitTypeDef.
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* @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that
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* contains a field PeriphClockSelection which can be a combination of the following values:
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* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_PVD PVD peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_COMP1 COMP1 peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_COMP2 COMP2 peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_LPTIM LPTIM peripheral clock (1)
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*
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* @note (1) Peripherals maybe not available on some devices
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* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
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* the RTC clock source: in this case the access to Backup domain is enabled.
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*
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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#if defined(RCC_BDCR_RTCSEL)
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uint32_t tickstart = 0U, temp_reg = 0U;
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FlagStatus pwrclkchanged = RESET;
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#endif
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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#if defined(RCC_BDCR_RTCSEL)
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/*------------------------------- RTC Configuration ------------------------*/
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if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
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{
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/* check for RTC Parameters used to output RTCCLK */
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assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
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/* As soon as function is called to change RTC clock source, activation of the
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power domain is done. */
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/* Requires to enable write access to Backup Domain of necessary */
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if (__HAL_RCC_PWR_IS_CLK_DISABLED())
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{
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__HAL_RCC_PWR_CLK_ENABLE();
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pwrclkchanged = SET;
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}
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if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
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{
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR1, PWR_CR1_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
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{
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if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
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temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
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if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
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{
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/* Store the content of BDCR register before the reset of Backup Domain */
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temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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/* RTC Clock selection can be changed only if the Backup Domain is reset */
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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/* Restore the Content of BDCR register */
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RCC->BDCR = temp_reg;
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#if defined(RCC_LSE_SUPPORT)
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/* Wait for LSERDY if LSE was enabled */
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if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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{
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if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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#endif
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}
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__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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/* Require to disable power clock if necessary */
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if (pwrclkchanged == SET)
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{
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__HAL_RCC_PWR_CLK_DISABLE();
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}
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}
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#endif /*RCC_BDCR_RTCSEL*/
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#if defined(RCC_CCIPR_PVDSEL)
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/*-------------------------- PVD clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PVD) == RCC_PERIPHCLK_PVD)
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{
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/* Check the parameters */
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assert_param(IS_RCC_PVDCLKSOURCE(PeriphClkInit->PvdClockSelection));
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/* Configure the PVD clock source */
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__HAL_RCC_PVD_CONFIG(PeriphClkInit->PvdClockSelection);
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}
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#endif /* RCC_CCIPR_PVDSEL */
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#if defined(RCC_CCIPR_COMP1SEL)
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/*-------------------------- COMP1 clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_COMP1) == RCC_PERIPHCLK_COMP1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_COMP1CLKSOURCE(PeriphClkInit->Comp1ClockSelection));
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/* Configure the COMP1 clock source */
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__HAL_RCC_COMP1_CONFIG(PeriphClkInit->Comp1ClockSelection);
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}
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_COMP2SEL)
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/*-------------------------- COMP2 clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_COMP2) == RCC_PERIPHCLK_COMP2)
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{
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/* Check the parameters */
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assert_param(IS_RCC_COMP2CLKSOURCE(PeriphClkInit->Comp2ClockSelection));
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/* Configure the COMP2 clock source */
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__HAL_RCC_COMP2_CONFIG(PeriphClkInit->Comp2ClockSelection);
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}
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#endif /* RCC_CCIPR_COMP2SEL */
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#if defined(RCC_CCIPR_LPTIMSEL)
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/*-------------------------- LPTIM clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM) == (RCC_PERIPHCLK_LPTIM))
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{
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assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->LptimClockSelection));
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__HAL_RCC_LPTIM_CONFIG(PeriphClkInit->LptimClockSelection);
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}
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#endif /* RCC_CCIPR_LPTIM1SEL */
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return HAL_OK;
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}
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/**
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* @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
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* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
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* returns the configuration information for the Extended Peripherals
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* clocks: PVD, COMP1, COMP2, RTC, LPTIM
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* @note Depending on devices and packages, some Peripherals may not be available.
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* Refer to device datasheet for Peripheral availability.
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* @retval None
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*/
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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/* Set all possible values for the extended clock type parameter------------*/
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#if defined(PY32F002APRE)
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PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_LPTIM;
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#else
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#if defined(RCC_CCIPR_PVDSEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_PVD;
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#endif
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#if defined(RCC_CCIPR_COMP1SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_COMP1;
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#endif
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#if defined(RCC_CCIPR_COMP2SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_COMP2;
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#endif
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#if defined(RCC_CCIPR_LPTIMSEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM;
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#endif
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#if defined(RCC_BDCR_RTCSEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_RTC;
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#endif
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#endif
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#if defined(RCC_CCIPR_PVDSEL)
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/* Get the PVD clock source ---------------------------------------------*/
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PeriphClkInit->PvdClockSelection = __HAL_RCC_GET_PVD_SOURCE();
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#endif /* RCC_CCIPR_PVDSEL */
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#if defined(RCC_CCIPR_COMP1SEL)
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/* Get the COMP1 clock source --------------------------------------------*/
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PeriphClkInit->Comp1ClockSelection = __HAL_RCC_GET_COMP1_SOURCE();
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_COMP2SEL)
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/* Get the COMP2 clock source ---------------------------------------------*/
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PeriphClkInit->Comp2ClockSelection = __HAL_RCC_GET_COMP2_SOURCE();
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#endif /* RCC_CCIPR_COMP2SEL */
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#if defined(RCC_CCIPR_LPTIMSEL)
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/* Get the LPTIM clock source ---------------------------------------------*/
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PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM_SOURCE();
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#endif /* RCC_CCIPR_LPTIM2SEL */
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#if defined(RCC_BDCR_RTCSEL)
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/* Get the RTC clock source ------------------------------------------------*/
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PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
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#endif /* RCC_BDCR_RTCSEL */
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}
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/**
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* @brief Return the peripheral clock frequency for peripherals with clock source from PLL
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* @note Return 0 if peripheral clock identifier not managed by this API
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* @param PeriphClk Peripheral clock identifier
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* This parameter can be one of the following values:
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* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
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* @arg @ref RCC_PERIPHCLK_PVD PVD peripheral clock
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* @arg @ref RCC_PERIPHCLK_COMP1 COMP1 peripheral clock
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* @arg @ref RCC_PERIPHCLK_COMP2 COMP2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_LPTIM LPTIM peripheral clock
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* @note Depending on devices and packages, some Peripherals may not be available.
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* Refer to device datasheet for Peripheral availability.
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* @retval Frequency in Hz
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*/
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uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
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{
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uint32_t frequency = 0U;
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uint32_t srcclk;
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#if defined(RCC_CCIPR_RNGSEL)
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uint32_t rngclk;
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uint32_t rngdiv;
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#endif
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
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#if defined(RCC_BDCR_RTCSEL)
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if (PeriphClk == RCC_PERIPHCLK_RTC)
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{
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/* Get the current RTC source */
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srcclk = __HAL_RCC_GET_RTC_SOURCE();
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/* Check if LSI is ready and if RTC clock selection is LSI */
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if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
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{
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frequency = LSI_VALUE;
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}
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#if defined(RCC_LSE_SUPPORT)
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/* Check if LSE is ready and if RTC clock selection is LSE */
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else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
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{
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frequency = LSE_VALUE;
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}
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#endif
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/* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
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else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) &&(srcclk == RCC_RTCCLKSOURCE_HSE_DIV128))
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{
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frequency = HSE_VALUE / 128U;
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}
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/* Clock not enabled for RTC*/
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else
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{
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/* Nothing to do as frequency already initialized to 0U */
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}
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}
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else
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{
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#endif
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/* Other external peripheral clock source than RTC */
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switch (PeriphClk)
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{
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#if defined(RCC_CCIPR_PVDSEL)
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case RCC_PERIPHCLK_PVD:
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/* Get the current PVD source */
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srcclk = __HAL_RCC_GET_PVD_SOURCE();
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if (srcclk == RCC_PVDCLKSOURCE_PCLK) /* PCLK1 */
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{
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frequency = HAL_RCC_GetPCLK1Freq();
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}
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#if defined(RCC_LSE_SUPPORT)
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else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (HAL_IS_BIT_CLR(RCC->BDCR, RCC_BDCR_LSCOSEL)) \
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&& (srcclk == RCC_PVDCLKSOURCE_LSC))
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{
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frequency = LSI_VALUE;
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}
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else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSCOSEL)) \
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&& (srcclk == RCC_PVDCLKSOURCE_LSC))
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{
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frequency = LSE_VALUE;
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}
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/* Clock not enabled for PVD */
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else
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{
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/* Nothing to do as frequency already initialized to 0U */
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}
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#else
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else
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{
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frequency = LSI_VALUE;
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}
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#endif
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break;
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#endif
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#if defined(RCC_CCIPR_COMP1SEL)
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case RCC_PERIPHCLK_COMP1:
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/* Get the current COMP1 source */
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srcclk = __HAL_RCC_GET_COMP1_SOURCE();
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if (srcclk == RCC_COMP1CLKSOURCE_PCLK) /* PCLK1 */
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{
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frequency = HAL_RCC_GetPCLK1Freq();
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}
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#if defined(RCC_LSE_SUPPORT)
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else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (HAL_IS_BIT_CLR(RCC->BDCR, RCC_BDCR_LSCOSEL)) \
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&& (srcclk == RCC_COMP1CLKSOURCE_LSC))
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{
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frequency = LSI_VALUE;
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}
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else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSCOSEL)) \
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&& (srcclk == RCC_COMP1CLKSOURCE_LSC))
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{
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frequency = LSE_VALUE;
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}
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/* Clock not enabled for COMP1 */
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else
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{
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/* Nothing to do as frequency already initialized to 0U */
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}
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#else
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else
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{
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frequency = LSI_VALUE;
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}
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#endif
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break;
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#endif
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#if defined(RCC_CCIPR_COMP2SEL)
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case RCC_PERIPHCLK_COMP2:
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/* Get the current COMP2 source */
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srcclk = __HAL_RCC_GET_COMP2_SOURCE();
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if (srcclk == RCC_COMP2CLKSOURCE_PCLK) /* PCLK1 */
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{
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frequency = HAL_RCC_GetPCLK1Freq();
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}
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#if defined(RCC_LSE_SUPPORT)
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else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (HAL_IS_BIT_CLR(RCC->BDCR, RCC_BDCR_LSCOSEL)) \
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&& (srcclk == RCC_COMP2CLKSOURCE_LSC))
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{
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frequency = LSI_VALUE;
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}
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else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSCOSEL)) \
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&& (srcclk == RCC_COMP2CLKSOURCE_LSC))
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{
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frequency = LSE_VALUE;
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}
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/* Clock not enabled for COMP2 */
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else
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{
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/* Nothing to do as frequency already initialized to 0U */
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}
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#else
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else
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{
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frequency = LSI_VALUE;
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}
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#endif
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break;
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#endif
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#if defined(RCC_CCIPR_LPTIMSEL)
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case RCC_PERIPHCLK_LPTIM:
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/* Get the current LPTIM1 source */
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srcclk = __HAL_RCC_GET_LPTIM_SOURCE();
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if (srcclk == RCC_LPTIMCLKSOURCE_PCLK)
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{
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frequency = HAL_RCC_GetPCLK1Freq();
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}
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else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIMCLKSOURCE_LSI))
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{
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frequency = LSI_VALUE;
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}
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#if defined(RCC_LSE_SUPPORT)
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else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIMCLKSOURCE_LSE))
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{
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frequency = LSE_VALUE;
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|
}
|
|
#endif
|
|
/* Clock not enabled for LPTIM1 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_LPTIM1SEL */
|
|
|
|
default:
|
|
break;
|
|
}
|
|
#if defined(RCC_BDCR_RTCSEL)
|
|
}
|
|
#endif
|
|
return (frequency);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
|
|
* @brief Extended Clock management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Extended clock management functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control the
|
|
activation or deactivation of LSE CSS, Low speed clock output and
|
|
clock after wake-up from STOP mode.
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Select the Low Speed clock source.
|
|
* @param LSCOSource specifies the Low Speed clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
|
|
* @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
FlagStatus backupchanged = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
|
|
|
|
/* Update LSCOSEL clock source in Backup Domain control register */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
pwrclkchanged = SET;
|
|
}
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
{
|
|
HAL_PWR_EnableBkUpAccess();
|
|
backupchanged = SET;
|
|
}
|
|
|
|
#if defined(RCC_BDCR_LSCOSEL)
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, LSCOSource);
|
|
#endif
|
|
|
|
if (backupchanged == SET)
|
|
{
|
|
HAL_PWR_DisableBkUpAccess();
|
|
}
|
|
if (pwrclkchanged == SET)
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
}
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT Puya *****END OF FILE****/
|